1. A memory system has a total of 8 memory chips, each with 12 address lines and 4 data lines. The total size of the memory system is
a) 16 Kbytes b) 48
Kbytes c) 32 Kbytes d) 64 Kbytes
Ans: Option a)
Each chip has 212 = 4096 x 4 bits
Capacity of 8 chips = 4096 x 4 x 8 = 16 Kbytes
Ans: Option a)
Each chip has 212 = 4096 x 4 bits
Capacity of 8 chips = 4096 x 4 x 8 = 16 Kbytes
2. What will be the size of memory address space for a 16 bit data and 20 bit address bus?
a) 1 MB b) 64 KB c) 2 MB d) None of these
Ans: Option a)
Size of memory address space depends on the address bus size.
220 = 1048576 = 1 MB
3. The memory address of last location of an 8 KB memory chip is FFFF H. Find the starting address.
a) F000 H b) E001 H c) E000 H d) F001 H
Ans: Option c)
4. A microprocessor is capable of addressing 64 K bytes of memory. Its address bus width is
a) 8 b) 16 c) 12 d) 20
Ans: Option b)
64 K = 2n
64 x 1024 = 2n
26 x 210 =
216
5. How many address lines are necessary to address 2 MB of
memory?
a) 21 b) 20 c) 22 d) 10
Ans: Option
a)
6. How many memory cells are there in a 128 x 4 memory chip?
a) 128 b) 512 c) 4 d) 1024
Ans: Option b)
7. An 8-bit microprocessor signifies that it has
a) An 8-bit address bus b) An 8 bit controller
c) 8-bit interrupt lines d) An 8 bit data bus
Ans: Option d)
8. In a microprocessor based system, the stack is always in
a) Microprocessor b) ROM c) RAM d) EPROM
Ans: Option c)
9. Which of the following statements is false?
a) A microprocessor has bi-directional address bus
b) A microprocessor has a unidirectional address bus
c) A microprocessor has bidirectional data bus
d) A microprocessor has an ALU
Ans: Option b)
10. A stack is
a) An 8 bit register in the microprocessor
b) An 16 bit register in the microprocessor
c) A set of memory locations in R/W memory reserved for storing information
d) An 16 bit memory address stored in the PC
Ans: Option c)
11. When a sub routine is called, the address of instruction following the CALL instruction is stored in/on the
a) Stack Pointer b) Accumulator c) Program Counter d) Stack
Ans: Option c)
12. The stack operates as
a) FIFO b) LILO c) LIFO d) None of these
Ans: Option c)
13. The data bus of any microprocessor is always
a) Unidirectional b) bi-directional c) Either unidirectional or bi-directional d) None of these
Ans: Option b)
14. Which one of the following is not a vectored interrupt?
a) TRAP b) RST 7.5 c) INTR d) RST3
Ans: Option a)
15. Identify the non-maskable interrupt from the following
a) RST 7.5 b) RST 5.5 c) RST 6.5 d) RST 4.5
Ans: Option d)
Except TRAP( RST 4.5), all other interrupts are maskable
16. The number of hardware interrupts present in 8085 microprocessor are
a) 5 b) 10 c) 8 d) 16
Ans: Option a)
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
17. An instruction which contains the data in it uses
a) Register Addressing b) Immediate Addressing c) Register Indirect Addressing d) Relative addressing
Ans: Option b)
18. The clock frequency of 8085 microprocessor is
a) 2 MHz b) 3 MHz c) 4 MHz d) 6 MHz
Ans: Option b)
19. The crystal frequency of 8085 microprocessor is
a) 2 MHz b) 3 MHz c) 4 MHz d) 6 MHz
Ans: Option d)
20. The addressing mode used in the instruction PUSH B is
a) direct b) register c) register indirect d) Immediate
Ans: Option c)
21. When any arithmetic instruction such as ADD or SUB is executed the condition flags
a) are always set b) are always reset c) are not affected d) are affected indicating specific conditions
Ans: Option d)
22. When any data transfer instruction, for transfer of data between memory and microprocessor, is executed the condition flags are
a) not affected b) always set c) always reset d) affected indicating specific conditions
Ans: Option a)
23. Which of the following flag condition are not available in 8085 microprocessor?
a) Zero Flag b) Parity Flag c) Overflow Flag d) Auxillary Flag
Ans: Option c)
24. Which of the following instruction will never affect the zero flag?
a) DCR reg. b) ORA reg. c) DCX reg. d) XRA reg.
Ans: Option c)
25. In a flag register of 8085, where does the sign flag and parity flag set?
a) D7 and D6 b) D6 and D4 c) D7 and D2 d) D7 and D4
6. How many memory cells are there in a 128 x 4 memory chip?
a) 128 b) 512 c) 4 d) 1024
Ans: Option b)
7. An 8-bit microprocessor signifies that it has
a) An 8-bit address bus b) An 8 bit controller
c) 8-bit interrupt lines d) An 8 bit data bus
Ans: Option d)
8. In a microprocessor based system, the stack is always in
a) Microprocessor b) ROM c) RAM d) EPROM
Ans: Option c)
9. Which of the following statements is false?
a) A microprocessor has bi-directional address bus
b) A microprocessor has a unidirectional address bus
c) A microprocessor has bidirectional data bus
d) A microprocessor has an ALU
Ans: Option b)
10. A stack is
a) An 8 bit register in the microprocessor
b) An 16 bit register in the microprocessor
c) A set of memory locations in R/W memory reserved for storing information
d) An 16 bit memory address stored in the PC
Ans: Option c)
11. When a sub routine is called, the address of instruction following the CALL instruction is stored in/on the
a) Stack Pointer b) Accumulator c) Program Counter d) Stack
Ans: Option c)
12. The stack operates as
a) FIFO b) LILO c) LIFO d) None of these
Ans: Option c)
13. The data bus of any microprocessor is always
a) Unidirectional b) bi-directional c) Either unidirectional or bi-directional d) None of these
Ans: Option b)
14. Which one of the following is not a vectored interrupt?
a) TRAP b) RST 7.5 c) INTR d) RST3
Ans: Option a)
15. Identify the non-maskable interrupt from the following
a) RST 7.5 b) RST 5.5 c) RST 6.5 d) RST 4.5
Ans: Option d)
Except TRAP( RST 4.5), all other interrupts are maskable
16. The number of hardware interrupts present in 8085 microprocessor are
a) 5 b) 10 c) 8 d) 16
Ans: Option a)
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
17. An instruction which contains the data in it uses
a) Register Addressing b) Immediate Addressing c) Register Indirect Addressing d) Relative addressing
Ans: Option b)
18. The clock frequency of 8085 microprocessor is
a) 2 MHz b) 3 MHz c) 4 MHz d) 6 MHz
Ans: Option b)
19. The crystal frequency of 8085 microprocessor is
a) 2 MHz b) 3 MHz c) 4 MHz d) 6 MHz
Ans: Option d)
20. The addressing mode used in the instruction PUSH B is
a) direct b) register c) register indirect d) Immediate
Ans: Option c)
21. When any arithmetic instruction such as ADD or SUB is executed the condition flags
a) are always set b) are always reset c) are not affected d) are affected indicating specific conditions
Ans: Option d)
22. When any data transfer instruction, for transfer of data between memory and microprocessor, is executed the condition flags are
a) not affected b) always set c) always reset d) affected indicating specific conditions
Ans: Option a)
23. Which of the following flag condition are not available in 8085 microprocessor?
a) Zero Flag b) Parity Flag c) Overflow Flag d) Auxillary Flag
Ans: Option c)
24. Which of the following instruction will never affect the zero flag?
a) DCR reg. b) ORA reg. c) DCX reg. d) XRA reg.
Ans: Option c)
25. In a flag register of 8085, where does the sign flag and parity flag set?
a) D7 and D6 b) D6 and D4 c) D7 and D2 d) D7 and D4
Ans: Option c)
26. Specify the number of times the given loop will count
LOOP: MVI B, 64 H
DCR B
JNZ LOOP
a) 101 b) 100 c) 65 d) infinite
Ans: Option d)
27. If the result has an odd number of 1s, what will happen to the parity flag
a) Set b) Reset c) Data insufficient d) None of these
Ans: Option b)
28. The instruction RST 7 is a
a) Restart instruction that begins the execution of a program
b) One-byte call to the memory address 0038 H
c) One-byte call to the memory address 0007 H
d) Hardware interrupt
Ans: Option b)
29. Which of the following instruction can be set to clear CY flag?
a) XRA A b) CLR c) AND A d) ADD A
Ans: Option a)
30. The number of status flags present in 8085 microprocessor are
a) 8 b) 5 c) 16 d) 10
Ans: Option b)
31. Let the contents of register C be 00000000 before DCR C is executed. The contents of the register after the execution of this instruction will be
a) 00000000 b) 00000001 c) 11111111 d) None
Ans: Option c)
32. PUSH B instruction in 8085 microprocessor causes
a) the contents of register B only to be copied in the stack
b) the contents of register B and C to be copied in the stack
c) the contents of register B and C to be transferred in the stack and the registers get cleared
d) Registers B and C to be cleared
Ans: Option b)
33. How many times the following loop will be executed?
26. Specify the number of times the given loop will count
LOOP: MVI B, 64 H
DCR B
JNZ LOOP
a) 101 b) 100 c) 65 d) infinite
Ans: Option d)
27. If the result has an odd number of 1s, what will happen to the parity flag
a) Set b) Reset c) Data insufficient d) None of these
Ans: Option b)
28. The instruction RST 7 is a
a) Restart instruction that begins the execution of a program
b) One-byte call to the memory address 0038 H
c) One-byte call to the memory address 0007 H
d) Hardware interrupt
Ans: Option b)
29. Which of the following instruction can be set to clear CY flag?
a) XRA A b) CLR c) AND A d) ADD A
Ans: Option a)
30. The number of status flags present in 8085 microprocessor are
a) 8 b) 5 c) 16 d) 10
Ans: Option b)
31. Let the contents of register C be 00000000 before DCR C is executed. The contents of the register after the execution of this instruction will be
a) 00000000 b) 00000001 c) 11111111 d) None
Ans: Option c)
32. PUSH B instruction in 8085 microprocessor causes
a) the contents of register B only to be copied in the stack
b) the contents of register B and C to be copied in the stack
c) the contents of register B and C to be transferred in the stack and the registers get cleared
d) Registers B and C to be cleared
Ans: Option b)
33. How many times the following loop will be executed?
LXI
B, 0007 H
LOOP: DCX
B
MOV A, B
ORA C
JNZ LOOP
a) 7 times b)
Cant say c) 8 times d) infinitely
Ans: Option
a)
34. The multiplexing of address bus and data buses is used in
microprocessors
a) To reduce the hardware complexity b) To increase the number of pins
c) To reduce the number of pins on IC d) To improve the operation
Ans: Option
c)
35. In a 8085 microprocessor based system, the contents of SP
are 1000 H. PUSH B instruction will transfer the contents of registers B and C
respectively for memory locations
a) OFFF H and OFFE H b)
1000 H and 0FFF H c) OFFE H
and OFFFH d) 1000 H and 1001
H
Ans: Option
a)
36. Intel 8085 is an
a) 8 bit NMOS processor b) 8 bit CMOS processor c) 8 bit PMOS processor d) 8 bit HMOS processor
Ans: Option a)
37. Which of the following is a 3 byte instruction?
a) LDA 2050 H b) MVI A, 32 H c) MOV C, A d) ADD B
Ans: Option a)
38. Which of the following devices is commonly used to interface O/P devices?
a) Latch b) Tristate buffer c) Both a) and b) d) None of these
Ans: Option a)
39. Which of the following devices is commonly used to interface I/P devices?
a) Latch b) Tristate buffer c) Both a) and b) d) None of these
Ans: Option b)
40. Specify the flag status (CY, S, Z) after the execution of instruction DRA.
36. Intel 8085 is an
a) 8 bit NMOS processor b) 8 bit CMOS processor c) 8 bit PMOS processor d) 8 bit HMOS processor
Ans: Option a)
37. Which of the following is a 3 byte instruction?
a) LDA 2050 H b) MVI A, 32 H c) MOV C, A d) ADD B
Ans: Option a)
38. Which of the following devices is commonly used to interface O/P devices?
a) Latch b) Tristate buffer c) Both a) and b) d) None of these
Ans: Option a)
39. Which of the following devices is commonly used to interface I/P devices?
a) Latch b) Tristate buffer c) Both a) and b) d) None of these
Ans: Option b)
40. Specify the flag status (CY, S, Z) after the execution of instruction DRA.
MVI
A, A9 H
MVI B, 57 H
ADD B
ORA A
a) 1,1,1 b)
0,1,0 c) 1,0,1 d) 1,1,0
Ans: Option
a)
41. Wait states are used
a) to give slow devices additional time to put out valid data b) to insert deliberate delay
c) during I/O operation d) none of the above
Ans: Option a)
42. READY signal in 8085 is useful when the CPU communicates with
a) a slow peripheral device b) a fast peripheral device
c) a DMA controller chi d) A PPI chip
Ans: Option a)
43. Direct-Memory-Access Channel (DMA) facilitates data to move into and out of system
a) on first-come-first-serve basis b) with equal time delay
c) with sub-routine d) without program intervention
Ans: Option d)
44. Return from subroutine is affected by
a) a jump instruction b) an RST instruction
c) a RET instruction d) a hardware interrupt signal
Ans: Option c)
45. In a generic microprocessor instruction cycle time is
a) shorter than machine cycle time b) larger than machine cycle time
c) exactly double the machine cycle time d) exactly the same as the machine cycle time
Ans: Option d)
46. The highest priority interrupt in 8085 microprocessor system is
a) RST 7.5 b) RST 6.5 c) INTR d) TRAP
Ans: Option d)
47. Which of the following statements is not applicable to serial transmission of data?
a) one bit at a time b) faster method of transmission
c) LSB transferred first d) only one wire used
Ans: Option b)
48. The three buses associated with three-bus system are I/O bus, memory bus and
a) address bus b) unibus c) direct memory access bus d) data bus
Ans: Option c)
49. The bus which is used to transfer data from main memory to peripheral device is
a) data bus b) input bus c) DMA bus d) output bus
Ans: Option c)
50. SHIFT LEFT instruction causes all bits shifted from one position to the left with rightmost bit set to zero. The effect is to
a) multiply by 2 b) divide by 2 c) SET the most significant bit d) none of the above
Ans: Option a)
51. Which of the following signal is used when a peripheral device request the microprocessor to have a DMA operation?
a) IO/M b) READY c) HOLD and HLDA d) RD and WR
Ans: Option c)
52. The output data lines of microprocessors and memories are usually tri-stated, because
a) More than one device can transmit information over the data bus by enabling only one device
b) More than one device can transmit information over the data bus at the same time
c) The data lines can be multiplexed for both input and output
d) It increases the speed of data transfers over the data bus
Ans: Option a)
53. Which of the following instruction copies a byte of data into the accumulator from the memory address given in the instruction?
a) LDA address b) LDAX B c) LHLD address d) STA address
Ans: Option a)
41. Wait states are used
a) to give slow devices additional time to put out valid data b) to insert deliberate delay
c) during I/O operation d) none of the above
Ans: Option a)
42. READY signal in 8085 is useful when the CPU communicates with
a) a slow peripheral device b) a fast peripheral device
c) a DMA controller chi d) A PPI chip
Ans: Option a)
43. Direct-Memory-Access Channel (DMA) facilitates data to move into and out of system
a) on first-come-first-serve basis b) with equal time delay
c) with sub-routine d) without program intervention
Ans: Option d)
44. Return from subroutine is affected by
a) a jump instruction b) an RST instruction
c) a RET instruction d) a hardware interrupt signal
Ans: Option c)
45. In a generic microprocessor instruction cycle time is
a) shorter than machine cycle time b) larger than machine cycle time
c) exactly double the machine cycle time d) exactly the same as the machine cycle time
Ans: Option d)
46. The highest priority interrupt in 8085 microprocessor system is
a) RST 7.5 b) RST 6.5 c) INTR d) TRAP
Ans: Option d)
47. Which of the following statements is not applicable to serial transmission of data?
a) one bit at a time b) faster method of transmission
c) LSB transferred first d) only one wire used
Ans: Option b)
48. The three buses associated with three-bus system are I/O bus, memory bus and
a) address bus b) unibus c) direct memory access bus d) data bus
Ans: Option c)
49. The bus which is used to transfer data from main memory to peripheral device is
a) data bus b) input bus c) DMA bus d) output bus
Ans: Option c)
50. SHIFT LEFT instruction causes all bits shifted from one position to the left with rightmost bit set to zero. The effect is to
a) multiply by 2 b) divide by 2 c) SET the most significant bit d) none of the above
Ans: Option a)
51. Which of the following signal is used when a peripheral device request the microprocessor to have a DMA operation?
a) IO/M b) READY c) HOLD and HLDA d) RD and WR
Ans: Option c)
52. The output data lines of microprocessors and memories are usually tri-stated, because
a) More than one device can transmit information over the data bus by enabling only one device
b) More than one device can transmit information over the data bus at the same time
c) The data lines can be multiplexed for both input and output
d) It increases the speed of data transfers over the data bus
Ans: Option a)
53. Which of the following instruction copies a byte of data into the accumulator from the memory address given in the instruction?
a) LDA address b) LDAX B c) LHLD address d) STA address
Ans: Option a)
9th answer will be option - (a) because address bus is unidirectional because data flow in one direction, from microprocessor to memory or from microprocessor to Input/output devices.
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