Monday, March 10, 2014

Do U Know?



  1. The minimum time delay between the initiations of two independent memory operations is called
a) access time               b)cycle time    c) transfer time  d) latency time

  1.   Which of the following comments are true?
    1. It is a register
    2. It is a cell in ROM
    3. During execution of the current instruction, its content changes
    4. None of the above

  1. Which of the following are registers?
a) Accumulator     b) Stack Pointer           c) Program counter       d) Buffer

  1.  A byte addressable computer has a memory capacity of 2m KB and can perform 2n operations. An instructions involving 3 operands and one operator needs a maximum of
a) 3m bits         b) 3m+n bits     c) m+n bits  d) none of these

 [Hints: To specify a particular operation, out of the 2n possible operations, one needs n bits. As the machine is byte addressable, to specify a particular byte we need (m+10) bits (2(n+10) bytes are there). So 3 addressable and 1 operations needs 3(m+10)+n=3m+n+30 bits] 

  1.   The number of columns in a state table for a sequential circuit with ‘m’ flip-flops and ‘n’ input is
    1. m+n     b) m+2n           c) 2m+n           d) 2m+2n
 [Hints: Present state + next state + input=m+m+n=2m+n]

  1. The addressing mode is used in an instruction of the form ADD X, Y is
    1. absolute          b) immediate     c) indirect         d) index

  1. How many 2 – input MUX are required to construct a 210 input MUX?
    1. 1023    b) 31    c) 10    d) 127

[A 2 –input MUX can select a single line out of the two – input lines. To select a signal line out of the 210, i.e, 1024 input lines, we have to use 1023 two – input MUX]

  1. Let A be a set having ‘n’ elements. The number of binary operations that can be defined on A is
    1.  

  1. The number of instructions needed to add ‘n’ numbers and store the results in memory using only one address instructions is
    1. n          b) n-1               c) n+1              d) independent of n

  1.  If memory access takes 20 ns with cache and 110 ns without it, then the hit – ratio (cache used a 10 ns memory) is
    1. 93%     b) 90%            c) 87%             d) 88%
[Hints: 20=10h+(1-h)110]

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